For example, loads such as various kinds of lamps, motors etc. mounted on a vehicle are coupled to a battery (power source) via semiconductor elements, whereby the operations of the loads are controlled by switching the on/off states of the corresponding semiconductor elements, respectively. An overcurrent may flow into a load circuit configured by such the battery, semiconductor elements and loads due to a trouble or an operational failure etc. of the load circuit or various kinds of circuits coupled to the load circuit. When the overcurrent flows, there arises a problem that the semiconductor elements are overheated and harness wires coupling between the loads and the power source are also overheated. Thus, various kinds of overcurrent protection apparatuses have been proposed each of which is arranged to immediately detect an overcurrent when the overcurrent is generated to thereby interrupt a current flowing into a load circuit.
FIG. 3 is a circuit diagram showing the configuration of a load circuit provided with an overcurrent protection apparatus of the related art. As shown in FIG. 3, the load circuit includes a series circuit formed by a battery VB, a MOSFET (T101) as a semiconductor element, and a load RL such as a lamp or a motor. The gate of the MOSFET (T101) is coupled to a driver circuit 101 via a resistor R110. Thus, the MOSFET (T101) is turned on and off in response to a drive signal outputted from the driver circuit 101 to thereby switch the load RL between a driving state and a stop state.
The drain of the MOSFET (T101) is coupled to a ground via a series circuit of resistors R104 and R105 and also coupled to the ground via a series circuit of a resistor R101, a transistor T102 and a resistor R103. A coupling point between the transistor T102 and the resistor R101 is coupled to the inverting input terminal of an amplifier AMP101 and the non-inverting input terminal of the amplifier AMP101 is coupled to the source of the MOSFET (T101). Further, the output terminal of the amplifier AMP101 is coupled to the gate of the transistor T102.
Further, a coupling point (voltage V3) between the transistor (T102) and the resistor R103 is coupled to the inverting input terminal of a comparator CMP101 and a coupling point (voltage V4) between the resistors R104 and R105 is coupled to the non-inverting input terminal of the comparator CMP101.
When the MOSFET (T101) is turned on and a current ID flows into the load circuit, a current I1 flows into the series circuit of the resistor R101, transistor T102 and resistor R103. In this case, the amplifier AMP101 controls the current I1 flowing into the transistor T102 so that the drain-source voltage Vds of the MOSFET (T101) becomes same as a voltage generated across the both ends of the resistor R101.
Thus, the voltage V3 generated at the resistor R103 becomes a value obtained by multiplying the voltage Vds by m (m=R103/R101). The amplified voltage V3 is inputted to the inverting input terminal of the comparator CMP101. The voltage V4 obtained by dividing a voltage V1 by the resistors R104 and R105 is inputted to the non-inverting input terminal of the comparator CMP101 as an overcurrent determination voltage. When the load current ID becomes an overcurrent state, the voltage Vds becomes large and so the voltage V3 becomes larger than the voltage V4. Thus, since the output state of the comparator CMP101 is inverted, the overcurrent state is detected.
Supposing that the drain voltage of the MOSFET (T101) is V1, the source voltage thereof is V2, the on-resistance thereof is Ron and the deviation of the on-resistance is ±ΔRon, the voltage Vds is represented by the following expression (1).Vds=V1−V2=(Ron±ΔRon)*ID  (1)
Thus, the voltage V3 is represented by the following expression (2).
                                                                        V                ⁢                                                                  ⁢                3                            =                            ⁢                              R                ⁢                                                                  ⁢                103                *                I                ⁢                                                                  ⁢                1                                                                                        =                            ⁢                                                (                                      R                    ⁢                                                                                  ⁢                                          103                      /                      R                                        ⁢                                                                                  ⁢                    101                                    )                                *                R                ⁢                                                                  ⁢                101                *                I                ⁢                                                                  ⁢                1                                                                                        =                            ⁢                              m                *                                  ID                  ⁡                                      (                                          Ron                      ±                                              Δ                        ⁢                                                                                                  ⁢                        Ron                                                              )                                                                                                          (        2        )            
Thus, since the voltage V3 contains a voltage obtained by multiplying (±ΔRon*ID) by m, this voltage causes the variance of a load current detection value.
Supposing that a value of the load current ID detected as an overcurrent is Iovc (hereinafter called as an “overcurrent detection value”), the following expression (3) is obtained.V3=m*(Ron*Iovc±ΔRon*Iovc)=V4  (3)
When the expression (3) is rewritten, the following expression (4) is obtained.Iovc=V4/m/Ron±ΔRon/Ron*Iovc  (4)
When the deviation ±ΔRon is not contained in the on-resistance Ron of the MOSFET (T101) (that is, ΔRon=0), the overcurrent detection value Iovc becomes a constant value determined by the voltage V4, resistor R101, resistor R103 and on-resistance Ron. However, when the on-resistance Ron of the MOSFET (T101) contains the deviation ±ΔRon, the overcurrent detection value Iovc varies and the variance value becomes “±ΔRon/Ron*Iovc”. The variance due to the deviation ΔRon is proportional to the overcurrent detection value Iovc.
In general, the value of ΔRon/Ron reaches in a range from 0.2 to 0.3, which largely degrades the detection accuracy when the voltage Vds is regarded as a current sensor. Thus, there has been increasing a demand of avoiding the influence of the deviation ΔRon by any means.
Further, in the case of changing the kind of the semiconductor element (MOSFET in the case of FIG. 3), since the on-resistance of the semiconductor element changes, it is necessary to change the determination voltage V4 in order to obtain a target overcurrent detection value Iovc. Thus, in the case of forming a circuit for controlling the semiconductor element as an integrated circuit, it becomes necessary not to dispose the resistors R104, R105 used for setting the determination voltage V4 within an integrated circuit but to dispose outside of the IC. As a result, the IC requires dedicated terminals for coupling with the resistors R104, R105, which results in the increase of an occupation space and cost-up.
Further, for example, JP-A-2002-353794 (patent document 1) is known as an example of the related arts which detects an overcurrent by avoiding the influence of the deviation ±ΔRon of the on-resistance Ron of the MOSFET (T101). The technique described in the patent document 1 relates to an overcurrent protection apparatus which intends to surely interrupt a circuit at the time of occurrence of a dead short-circuit but does not intend to surely detect a current of an overcurrent determination value Iovc when the current flows into the load RL.